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these bits are cleared (SP=0), indicating that the SS is empty.
Data is pushed onto the SS by incrementing the SP, then writing data to the location to
which the SP points. An item is pulled off the stack by copying it from that location and
then by decrementing the SP.
5.4.5.2
Stack Error Flag (Bit 4)
The stack error flag indicates that a stack error has occurred, and the transition of the
stack error flag from zero to one causes a priority level-3 stack error exception.
When the stack is completely full, the SP reads 001111, and any operation that pushes
data onto the stack will cause a stack error exception to occur. The SR will read 010000
(or 010001 if an implied double push occurs).
Any implied pull operation with SP equal to zero will cause a stack error exception, and
the SP will read 111111 (or 111110 if an implied double pull occurs).
The stack error flag is a "sticky bit" which, once set, remains set until cleared by the user.
There is a sequence of instructions that can cause a stack overflow and, without the sticky
bit, would not be detected because the stack pointer is decremented before the stack error
interrupt is taken. The sticky bit keeps the stack error bit set until the user clears it by writ-
ing a zero to SP bit 4. It also latches the overflow/underflow bit so that it cannot be
changed by stack pointer increments or decrements as long as the stack error is set. The
overflow/underflow bit remains latched until the first move to SP is executed.
Note:
When SP is zero (stack empty), instructions that read the stack without SP post-
decrement and instructions that write to the stack without SP preincrement do not cause
a stack error exception (i.e., 1) DO SSL,xxxx 2) REP SSL 3) MOVEC or move peripheral
UF SE P3 P2 P1 P0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
5 - 16
PROGRAMMING MODEL
1
1
1
0
STACK UNDERFLOW CONDITION AFTER DOUBLE PULL
1
1
1
1
STACK UNDERFLOW CONDITION
0
0
0
0
STACK EMPTY (RESET); PULL CAUSES UNDERFLOW
0
0
0
1
STACK LOCATION 1
1
1
1
0
STACK LOCATION 14
1
1
1
1
STACK LOCATION 15; PUSH CAUSES OVERFLOW
0
0
0
0
STACK OVERFLOW CONDITION
0
0
0
1
STACK OVERFLOW CONDITION AFTER DOUBLE PUSH
Figure 5-8 SP Register Values
PROGRAM CONTROL UNIT
MOTOROLA
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