Interrupt Priority Structure; Interrupt Priority Levels (Ipl); Exception Priorities Within An Ipl; Memory Organization - Motorola DSP56156 Manual

bit PC can address 65,536 locations in program memory space. See the DSP56100 Fam-
ily Manual for additional information.
1.2.5.1

Interrupt Priority Structure

Four levels of interrupt priority are provided. Interrupt priority levels (IPLs) numbered 0, 1,
and 2, are maskable with level 0 as the lowest level. Level 3 (the highest level), is non-
maskable. The only level 3 interrupts are Reset, Illegal Instruction, Stack Error and SWI.
The interrupt mask bits (I1, I0) in the status register reflect the current processor priority
level and indicate the interrupt priority level needed for an interrupt source to interrupt the
processor (see Table 1-2). Interrupts are inhibited for all priority levels less than the cur-
rent processor priority level. However, level 3 interrupts are not maskable and therefore
can always interrupt the processor.
1.2.5.2

Interrupt Priority Levels (IPL)

The interrupt priority level for each on-chip peripheral device and for each external interrupt
source (IRQA, IRQB) can be programmed under software control. Each on-chip or external
peripheral device can be programmed to one of the three maskable priority levels (IPL 0, 1,
or 2). Interrupt priority levels are set by writing to the Interrupt Priority Register shown in Fig-
ure 1-8. This read/write register specifies the interrupt priority level for each of the interrupt-
ing devices (Codec, Host, SSIs, Timer, IRQA, IRQB). In addition, this register specifies the
trigger mode of both external interrupt sources and it is used to enable or disable the indi-
vidual external interrupts. This register is cleared on RESET. Table 1-3 defines the interrupt
priority level bits. Table 1-4 defines the external interrupt trigger mode bits.
1.2.5.3

Exception Priorities within an IPL

If more than one exception is pending when an instruction is executed, the interrupt with the
highest priority level is serviced first. When multiple interrupt requests with the same IPL are
pending, a second fixed priority structure within that IPL determines which interrupt is ser-
viced. The fixed priority of interrupts within an IPL and the interrupt enable bits for all inter-
rupts are shown in Table 1-5. The interrupt enable bits for the Host, SSIs, and TM are
located in the control registers associated with their respective on-chip peripherals.
1.3

MEMORY ORGANIZATION

Two independent memory spaces of the DSP56156 — X data and program, are described
in detail in Section 3. These memory spaces are configured by control bits in the Operat-
ing Mode Register. MA and MB control the program memory map and select the reset
vector address.
MOTOROLA

MEMORY ORGANIZATION

DSP56156 OVERVIEW 1 - 17