EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
Table 7-2 Status Register Interrupt Mask Bits
ority levels, see the individual DSP56K family member's User's Manual.
126.96.36.199 Interrupt Priority Levels
The IPL for each on-chip peripheral device (HI, SSI, SCI) and for each external interrupt
source (IRQA, IRQB) can be programmed to one of the three maskable priority levels
(IPL 0, 1, or 2) under software control. IPLs are set by writing to the interrupt priority reg-
ister shown in Figure 7-2. This read/write register is located in program memory at
address $FFFF. It specifies the IPL for each of the interrupting devices including IRQA,
IRQB and each peripheral device. (For specific peripheral information, see the specific
DSP56K family member's User's Manual.) In addition, it specifies the trigger mode of the
external interrupt sources and is used to enable or disable the individual external inter-
rupts. The interrupt priority register is cleared on RESET or by the reset instruction.
Table 7-3 defines the IPL bits. Table 7-4 defines the external interrupt trigger mode bits.
188.8.131.52 Exception Priorities Within an IPL
If more than one interrupt is pending when an instruction is executed, the processor will
service the interrupt with the highest priority level first. When multiple interrupt requests
Bits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility.
Figure 7-2 Interrupt Priority Register (Addr X:$FFFF)
7 - 14
IPL 0, 1, 2, 3
IPL 1, 2, 3
IPL 2, 3
IPL 0, 1
IPL 0, 1, 2
RESERVED FOR EXPANSION
RESERVED FOR PERIPHERAL IPL LEVELS