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L (Limit Bit)
E (Extension Bit)
Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accumulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scal-
ing mode being used. The extension register portion of an accumulator (A2 or B2) is always the MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accumulator and NOT the extension register portion of that accumulator. For
example, if the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of the A or B accumulator consists of bits 47 through 55 . If the A accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data ALU oper-
ation , the E bit would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., neither 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. This limiting
operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. The only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same
is in the ''Scale Down'' scaling mode (i.e., S1=0 and S0=1).
U (Unnormalized Bit)
N (Negative Bit)
Z (Zero Bit)
V (Overflow Bit)
C (Carry Bit)
Table A-5 details how each instruction affects the condition codes. The convention for the notation that is used is shown at the bottom of Table A-5.
A.5
PARALLEL MOVE DESCRIPTIONS
Many of the instructions in the DSP56000/DSP56001 instruction set allow optional parallel data bus movement. A.6 INSTRUCTION DESCRIPTIONS indicates the parallel move option in the instruction syntax with the statement ''(parallel move)''. The MOVE instruc-
tion is equivalent to a NOP with parallel moves. Therefore, a detailed description of each parallel move is given with the MOVE instruction details in A.6 INSTRUCTION DESCRIPTIONS.
A.6
INSTRUCTION DESCRIPTIONS
The following section describes each instruction in the DSP56000/DSP56001 instruction set in complete detail. The format of each instruction description is given in A.1 INSTRUCTION GUIDE. Instructions which allow parallel moves include the notation ''(parallel
move)'' in both the Assembler Syntax and the Operation fields. The example given with each instruction discusses the contents of all the registers and memory locations referenced by the opcode-operand portion of that instruction but not those referenced by the
parallel move portion of that instruction. Refer to A.5 PARALLEL MOVE DESCRIPTIONS for a complete discussion of parallel moves, including examples which discuss the contents of all the registers and memory locations referenced by the parallel move portion of
an instruction.
Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation, the parallel move operation will use the value in the accumulator prior to execution of any data ALU operation.
Whenever a bit in the condition code register is defined according to the standard definition given in A.4 CONDITION CODE COMPUTATION, a brief definition will be given in normal text in the Condition Code section of that instruction description. Whenever a bit
in the condition code register is defined according to a special definition for some particular instruction, the complete special definition of that bit will be given in the Condition Code section of that instruction in bold text to alert the user to any special conditions con-
cerning its use.
MOTOROLA
Freescale Semiconductor, Inc.
Set if the overflow bit V is set or if the data shifter/limiters perform a limiting operation. Not affected otherwise. This bit is latched and must be reset by the user.
Cleared if all the bits of the signed integer portion of the A or B result are the same =m i.e., the bit patterns are either 00 . . . 00 or 11 . . . 11. Set otherwise. The signed integer portion is defined
by the scaling mode as shown in the following table:
S1
S0
Scaling Mode
0
0
No Scaling
0
1
Scale Down
1
0
Scale Up
Set if the two MS bits of the MSP portion of the A or B result are the same. Cleared otherwise. The MSP portion is defined by the scaling mode. The U bit is computed as follows:
S1
S0
Scaling Mode
0
0
No Scaling
0
1
Scale Down
1
0
Scale Up
Set if the MS bit 55 of the A or B result is set. Cleared otherwise.
Set if the A or B result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurs in the 56-bit A or B result. This indicates that the result cannot be represented in the 56-bit accumulator; thus, the accumulator has overflowed. Cleared other-
wise.
Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction. The carry or borrow is generated out
of bit 55 of the A or B result. Cleared otherwise.
DSP56000/DSP56001 USER'S MANUAL
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Signed Integer Portion
Bits 55, 54, . . . . 48, 47
Bits 55, 54, . . . . 49, 48
Bits 55, 54, . . . . 47, 46
U Bit Computation
U=(Bit 47 ⊕ Bit 46)
U=(Bit 48 ⊕ Bit 47)
U=(Bit 46 ⊕ Bit 45)
A - 11
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