Icr Hi Flag 1 (Hf1)-Bit 4; Icr Hi Mode Control (Hm1 And Hm0)-Bits 5 And 6; Figure 4-12 Hsr And Hcr Operation; Table 4-3 Hi Mode Bit Definition - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
7
X:$FFE8 0 0
7
X:$FFE9
DMA 0
4.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 4
The HI Flag 1 (HF1) bit is used as a general purpose flag for host-to-DSP
communication. HF1 can be set or cleared by the host processor and cannot be
changed by the DSP.
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF1.
4.4.5.3.6 ICR HI Mode Control (HM1 and HM0)—Bits 5 and 6
The HI Mode Control 1 (HM1) and HI Mode Control 0 (HM0) bits select the transfer
mode of the HI (see Table 4-3). HM1 and HM0 enable the DMA mode of operation
or the Interrupt (non-DMA) mode of operation.
4-26
0 HF3 HF2 HCIE HTIE HRIE
0 HF1 HF0 HCP HTDE HRDF

Figure 4-12 HSR and HCR Operation

Table 4-3 HI Mode Bit Definition

HM1 HM0
0 0
0 1
1 0
1 1
DSP56012 User's Manual
Mask
0
HCR
Receive Data Full
P:$0030
Transmit Data Empty
P:$0032
Host Command
P:(2
Reset
0
HSR
Status
Mode
Interrupt Mode (DMA Off)
DMA Mode (24-bit)
DMA Mode (16-bit)
DMA Mode (8-bit)
DSP CPU Interrupts
HV $0000–$007E)
HV = $0017 in CVR
AA0317.11
MOTOROLA