Instruction Cache Enabled (0, 0, 1) - Motorola DSP56303 User Manual

24-bit digital signal processor
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Memory Maps
Program
$FFFFFF
Internal
Reserved
$FFF0C0
Bootstrap ROM
$FF0000
External
$000C00
Internal
Program RAM
$000000
Bit Settings
SC
MS
CE
0
0
1
3-8
$FFFFFF
Internal I/O
$FFFF80
$FFF000
$FF0000
$000800
X data RAM
3 K
$000000
Program RAM
X Data RAM
3 K
2 K
$000–$BFF
$000–$7FF
Figure 3-2. Instruction Cache Enabled (0, 0, 1)
DSP56303 User's Manual
X Data
$FFFFFF
$FFFF80
External
$FFF000
Internal
Reserved
$FF0000
External
$000800
Internal
2 K
$000000
Memory Configuration
Y Data RAM
2 K
$000–$7FF
Y Data
External I/O
External
Internal
Reserved
External
Internal
Y data RAM
2 K
Addressable
Cache
Memory Size
1 K
16 M
internal not
accessible

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