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Table 1-2 Interrupt Starting Addresses and Sources (Continued)
Interrupt
Starting Address
P: $004A
P: $004C
:
P: $007E
1.3.3.2
X Data Memory
The on-chip X data memory is 24 bits wide. Addresses are received from the XAB,
and data transfers to the Data ALU occur on the XDB.
1.3.3.3
Y Data Memory
The on-chip Y data memory is 24 bits wide. Addresses are received from the YAB,
and data transfers to the Data ALU occur on the YDB.
1.3.3.4
On-Chip Memory Configuration Bits
Through the use of bits PEA and PEB in the OMR, four different memory
configurations are possible. These configurations provide appropriate memory sizes
for a variety of applications (see Table 1-3). Section 3 provides detailed information
about memory configuration.
Program RAM
X data RAM
Y data RAM
Program ROM
X data ROM
Y data ROM
1.3.3.5
Bootstrap ROM
The bootstrap ROM occupies locations 0–31 ($0–$1F) and 256–287 ($100–$11F) in two
areas in the memory map on the DSP56009. The bootstrap ROM is
factory-programmed to perform the bootstrap operation following hardware reset; it
either jumps to the user's ROM starting address (P:$2000) or downloads up to 512
words of user program from either the EMI port or the SHI port (in SPI or I
format). The bootstrap ROM activity is controlled by the bits MA, MB, and MC,
MOTOROLA
IPL
0–2
SAI Receiver Exception if RXIL = 1
Reserved
:
Reserved
Table 1-3 Internal Memory Configurations
No Switch
Switch A
(PEA = 0,
(PEA = 1,
PEB = 0)
PEB = 0)
0.5 K
4.5 K
4.25 K
10.0 K
3.0 K
1.75 K
DSP56009 User's Manual
DSP56009 Architectural Overview
Interrupt Source
Switch B
(PEA = 0,
PEB = 1)
1.25 K
2.0 K
3.75 K
3.75 K
4.25 K
3.5 K
10.0 K
10.0 K
3.0 K
3.0 K
1.75 K
1.75 K
Overview
Switch A + B
(PEA = 1,
PEB = 1)
2.75 K
3.0 K
3.5 K
10.0 K
3.0 K
1.75 K
2
C
1-15
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