Data Memory; Y Data Memory; On-Chip Memory Configuration Bits; Table 1-4 Internal Memory Configurations - Motorola DSP56012 User Manual

Table 1-3 Interrupt Starting Addresses and Sources (Continued)
Interrupt
Starting Address
P: $0050
P: $0052
P: $0054
P: $0056
P: $0058
:
P: $007E
1.3.3.2 X Data Memory
The on-chip X data memory shown in Table 1-4 is 24 bits wide. Addresses are
received from the XAB, and data transfers to the Data ALU occur on the XDB.
1.3.3.3

Y Data Memory

The on-chip Y data memory shown in Table 1-4 is 24 bits wide. Addresses are
received from the YAB, and data transfers to the Data ALU occur on the YDB.
1.3.3.4

On-Chip Memory Configuration Bits

Through the use of bits PEA and PEB in the OMR, four different memory
configurations are possible. These configurations provide appropriate memory sizes
for a variety of applications (see Table 1-4). Section 3 provides detailed information
about memory configuration.
Program RAM
X RAM
Y RAM
Program ROM
X ROM
Y ROM
MOTOROLA
IPL
0–2 DAX Transmit Underrun Error
0–2 DAX Block Transferred
Reserved; available for Host Command, see p. B-5–B-6.
0–2 DAX Transmit Register Empty
Reserved; available for Host Command, see p. B-5–B-6.
Reserved; available for Host Command, see p. B-5–B-6.
Reserved; available for Host Command, see p. B-5–B-6.

Table 1-4 Internal Memory Configurations

No Switch Switch A
(PEA = 0 (PEA = 1
PEB = 0) PEB = 0)
0.25 K
4.0 K
4.25 K
15 K
3.5 K
2.0 K
DSP56012 User's Manual
DSP56012 Architectural Overview
Interrupt Source
Switch B
(PEA = 0
PEB = 1)
1.0 K 1.75 K
3.25 K 3.25 K
4.25 K 3.5 K
15 K 15 K
3.5 K 3.5 K
2.0 K 2.0 K
Overview
Switch A+B
(PEA = 1
PEB = 1)
2.5 K
2.5 K
3.5 K
15 K
3.5 K
2.0 K
1-15