ST STM32L4+ Series Reference Manual page 2051

RM0432
EMPTY
FMP=0x00
FOVR=0
FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the
CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox.
The software reads out the mailbox content and releases it by setting the RFOM bit in the
CAN_RFR register. The FIFO becomes empty again. If a new valid message has been
received in the meantime, the FIFO stays in pending_1 state and the new message is
available in the output mailbox.
If the application does not release the mailbox, the next valid message will be stored in the
FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for
the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this
point, the software must release the output mailbox by setting the RFOM bit, so that a
mailbox is free to store the next valid message. Otherwise the next valid message received
will cause a loss of message.
Refer also to
Figure 608. Receive FIFO states
Valid Message
Received
Release
Mailbox
Release
Mailbox
RFOM=1
Release
Mailbox
RFOM=1
Section 55.7.5: Message storage
RM0432 Rev 6
Controller area network (bxCAN)
PENDING_1
FMP=0x01
FOVR=0
Valid Message
Received
PENDING_2
FMP=0x10
FOVR=0
Valid Message
Received
PENDING_3
Valid Message
FMP=0x11
FOVR=0
Received
Release
Mailbox
RFOM=1
OVERRUN
FMP=0x11
FOVR=1
Valid Message
Received
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