Low-Power Modes - STMicroelectronics STM32WLEx Reference Manual

RM0461
5.4

Low-power modes

By default, the microcontroller is in Run mode after a system or a power reset. Low-power
modes are available to save power when the CPU does not need to be kept running, for
example when it is waiting for an external event. The user must select the mode giving the
best compromise between consumption, startup time and available wakeup sources.
These low-power modes are detailed below:
•
Sleep
them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event
occurs.
•
Low-power run mode
2 MHz. The code is executed from the SRAM or from the flash memory. The regulator
is in low-power mode to minimize the operating current.
•
Low-power sleep mode
• Stop 0
retained. All clocks in the V
disabled. LSI and LSE can be kept running.
RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz
radio may remain active independently from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop
mode to detect their wakeup condition.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption compared with Stop 2.
In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but
with much higher consumption. The active peripherals and wakeup sources are the
same as in Stop 1 mode that uses the low-power regulator.
The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz
or HSI16, depending on the software configuration.
•
Stop 2
and some peripherals preserve their contents (see
on system operating
All clocks in the V
LSI and LSE can be kept running.
RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The sub-
GHz radio may also remain active independent from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2
mode to detect their wakeup condition (see
system operating
The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or
HSI16, depending on the software configuration.
•
Standby
SRAM2 content as detailed below:
–
–
mode: CPU clock off, all peripherals including CPU core peripherals (among
(LPRun): when the system clock frequency is reduced below
(LPSleep): entered from the LPRun mode.
mode, and Stop 1 mode: the content of SRAM1, SRAM2 and of all registers is
mode: part of the V
mode).
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
CORE
mode) .
mode: V domain is powered off. However, it is possible to preserve the
CORE
Standby mode with SRAM2 retention when the RRS bit is set in the
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
Standby mode when the RRS bit is cleared in the
(PWR_CR3). In this case the main regulator and the low-power regulator are
domain are stopped. PLL, MSI, HSI16 and HSE32 are
CORE
domain is powered off. Only SRAM1, SRAM2, CPU
CORE
Table 37: Functionalities depending on
RM0461 Rev 5
Power control (PWR)
Table 37: Functionalities depending
PWR control register 3
PWR control
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