Figure 111. Dma Transfer Of A 128-Bit Data Block During Input Phase - STMicroelectronics STM32WLEx Reference Manual

RM0461
21.4.16 AES DMA interface
The AES peripheral provides an interface to connect to the DMA (direct memory access)
controller. The DMA operation is controlled through the AES_CR register.
Data input using DMA
Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES
peripheral then initiates a DMA request during the input phase each time it requires to write
a 128-bit block (quadruple word) to the AES_DINR register, as shown in
Note: According to the algorithm and the mode selected, special padding / ciphertext stealing
might be required. For example, in case of AES GCM encryption or AES CCM decryption, a
DMA transfer must not include the last block. For details, refer to
procedure to perform a cipher

Figure 111. DMA transfer of a 128-bit data block during input phase

Word3
DIN[127:96]
D127
MSB
DMA
DMA req N
single write
1
(No swapping)
1
I127
MSB
1 4
Order of write to AES_DINR
Data output using DMA
Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The
AES peripheral then initiates a DMA request during the Output phase each time it requires
to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in
Note: According to the message size, extra bytes might need to be discarded by application in the
last block.
operation.
Chronological order
Increasing address
Memory accessed through DMA
Word2
DIN[95:64]
D96 D95
DMA
DMA req N+1
single write
2
2
AES core input buffer
I96 I95
Word1
DIN[63:32]
D64 D63
DMA
DMA req N+2
single write
3
AES_DINR
3
I64 I63
RM0461 Rev 5
AES hardware accelerator (AES)
Figure
Section 21.4.4: AES
Word0
DIN[31:0]
D32 D31
DMA
DMA req N+3
single write
4
4
I32 I31
111.
D0
LSB
I0
LSB
MSv42160V1
Figure 112.
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