Table 78. Vector Table - STMicroelectronics STM32WLEx Reference Manual

Nested vectored interrupt controller (NVIC)
13 Nested vectored interrupt controller (NVIC)
13.1 NVIC main features
•
62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt
lines)
•
16 programmable priority levels (four bits of interrupt priority used)
•
Low-latency exception interrupt handling
•
Power management control
• Implementation of system control registers
The NVIC and the processor core interfaces are closely coupled, resulting in low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC.
For more information on exceptions and NVIC programming, refer to the PM0214
programming manual for Cortex
13.2 Interrupt and exception vectors
The vector table is given in
Type of
priority
- - -
- -3 Fixed
- -2 Fixed
- -1 Fixed
- 0 Settable MemManager
- 1 Settable
- 2 Settable
- - -
- 3 Settable
- 4 Settable
- - -
- 5 Settable
- 6 Settable
0 7 Settable
400/1306
Table 78

Table 78. Vector table

Acronym
- Reserved
Reset Reset
Non maskable interrupt HSE32 CSS, Flash ECC and
NMI
SRAM2 parity
HardFault All classes of fault
Memory manager
BusFault Prefetch fault, memory access fault
UsageFault Undefined instruction or illegal state
- Reserved
SVCall System service can via SWI instruction
Debug Debug monitor
- Reserved
PendSV Pendable request for system service
SysTick SysTick timer
WWDG Window watchdog early wakeup
®
-M4 (PM0214).
(shaded cells indicate the processor exceptions).
Description
RM0461 Rev 5
(1)
RM0461
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0014
0x0000 0018
0x0000 001C
0x0000 0028
0x0000 002C
0x0000 0030
0x0000 0034
0x0000 0038
0x0000 003C
0x0000 0040