STMicroelectronics STM32WLEx Reference Manual page 282

Reset and clock control (RCC)
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN: Low-power timer 3 clock enable during Sleep and Stop modes
Bit 5 LPTIM2SMEN: Low power timer 2 clock enable during Sleep and Stop modes
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1SMEN: Low-power UART 1 clock enable during Sleep and Stop modes
6.4.27 RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR)
Address offset: 0x080
Reset value: 0x0006 5A00
Access: word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART1 SPI1
Res. Res.
SMEN SMEN
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: Timer 17 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM17 clock disabled by the clock gating during Sleep and Stop modes
1: TIM17 clocks enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 17 TIM16SMEN: Timer 16 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM16 clock disabled by the clock gating during Sleep and Stop modes
1: TIM16 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 16:15 Reserved, must be kept at reset value.
282/1306
This bit is set and cleared by software.
0: LPTIM3 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM3 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: LPTIM2 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPTIM2 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
This bit is set and cleared by software.
0: LPUART1 bus clock disabled by the clock gating during Sleep and Stop modes
1: LPUART1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM1 ADC
Res.
SMEN SMEN
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0461 Rev 5
21 20 19 18
TIM17
Res. Res. Res.
SMEN
rw
5 4 3 2
Res. Res. Res. Res.
RM0461
17 16
TIM16
Res.
SMEN
rw
1 0
Res. Res.