STMicroelectronics STM32WLEx Reference Manual page 300

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Hardware semaphore (HSEM)
7.3.6
HSEM MASTERID semaphore clear
All semaphores locked by a MASTERID can be unlocked at once by using the HSEM_CR
register. Write MASTERID and correct KEY value in HSEM_CR. All locked semaphores with
a matching MASTERID are unlocked, and may generate an interrupt when enabled.
An interrupt may be generated for the unlocked semaphore(s). To this end, the semaphore
interrupt must be enabled in the HSEM_IER register.
7.3.7
HSEM interrupts
An interrupt line hsem_int_it allows each semaphore to generate an interrupt.
An interrupt line provides the following features per semaphore:
interrupt enable
interrupt clear
interrupt status
masked interrupt status
With the interrupt enable (HSEM_IER) the semaphores affecting the interrupt line can be
enabled. Disabled (masked) semaphore interrupts do not set the masked interrupt status
MISF for that semaphore, and do not generate an interrupt on the interrupt line.
The interrupt clear (HSEM_ICR) clears the interrupt status ISF and masked interrupt status
MISF of the associated semaphore for the interrupt line.
The interrupt status (HSEM_ISR) mirrors the semaphore interrupt status ISF before the
enable.
The masked interrupt status (HSEM_MISR) only mirrors the semaphore enabled interrupt
status MISF on the interrupt line. All masked interrupt status MISF of the enabled
semaphores need to be cleared to clear the interrupt line.
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RM0461 Rev 5
RM0461

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