STMicroelectronics STM32WLEx Reference Manual page 101

RM0461
Bit 26 nSWBOOT0: software BOOT0 selection
Bit 25 SRAM_RST: SRAM1 and SRAM2 erase when system reset
Note: PKA SRAM is always erased on any system.
Bit 24 SRAM2_PE: SRAM2 parity check enable
Bit 23 nBOOT1: boot configuration
Bits 22:20 Reserved, must be kept at reset value.
Bit 19 WWDG_SW: window watchdog selection
Bit 18 IWDG_STDBY: independent watchdog counter freeze in Standby mode
Bit 17 IWDG_STOP: independent watchdog counter freeze in Stop mode
Bit 16 IWDG_SW: independent watchdog selection
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW: reset generation in Shutdown mode
Bit 13 nRST_STDBY: reset generation in Standby mode
Bit 12 nRST_STOP: reset generation in Stop mode
Bits 11:9 BOR_LEV[2:0]: BOR reset Level
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
0: SRAM1 and SRAM2 erased when a system reset occurs
1: SRAM1 and SRAM2 not erased when a system reset occurs
0: SRAM2 parity check enabled
1: SRAM2 parity check disable
Together with the BOOT0 pin or option bit nBOOT0 (depending on nSWBOOT0 option bit
configuration), this bit selects boot mode from the user flash memory, SRAM or system
flash memory. Refer to Section 2.2: Boot
0: Hardware window watchdog
1: Software window watchdog
0: Independent watchdog counter frozen in Standby mode
1: Independent watchdog counter running in Standby mode
0: Independent watchdog counter frozen in Stop mode
1: Independent watchdog counter running in Stop mode
0: Hardware independent watchdog
1: Software independent watchdog
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
0: Reset generated when entering the Standby mode
1: No reset generated when entering the Standby mode
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
These bits contain the V
000: BOR level 0. Reset level threshold is around 1.7 V
001: BOR level 1. Reset level threshold is around 2.0 V
010: BOR level 2. Reset level threshold is around 2.2 V
011: BOR level 3. Reset level threshold is around 2.5 V
100: BOR level 4. Reset level threshold is around 2.8 V
configuration.
supply level threshold that activates/releases the reset.
DD
RM0461 Rev 5
Embedded flash memory (FLASH)
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