Pwr Sub-Ghz Spi Control Register (Pwr_Subghzspicr) - STMicroelectronics STM32WLEx Reference Manual

RM0461
Bit 10 C1STOPF: System Stop 0, 1 flag for CPU (all core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 0 or 1 mode
1: System has been in Stop 0 or 1 mode.
Bit 9 C1STOP2F: System Stop 2 flag for CPU (partial core states retained)
This bit is set by hardware and cleared only by any reset or by setting C1CSSF bit.
0: System has not been in Stop 2 mode
1: System has been in Stop 2 mode.
Bit 8 C1SBF: System Standby flag for CPU (no core states retained)
This bit is set by hardware and cleared only by a POR reset or by setting C1CSSF bit.
0: System has not been in Standby mode
1: System has been in Standby mode.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 C1CSSF: Clear CPU Stop Standby flags
Setting this bit clears the C1STOPF and C1SBF bits.
5.5.18

PWR sub-GHz SPI control register (PWR_SUBGHZSPICR)

Address offset: 0x090
Reset value: 0x0000 8000
31 30 29
Res. Res. Res. Res.
15 14 13
NSS Res. Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 NSS: sub-GHz SPI NSS control
This bit is set and cleared by software and is used to control the sub-GHz SPI NSS level from
software.
0: sub-GHz SPI NSS signal at level low
1: sub-GHz SPI NSS signal is at level high
Bits 14:0 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0461 Rev 5
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
Res. Res.
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229