RM0461
19.6
COMP registers
19.6.1
COMP1 control and status register (COMP1_CSR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
LOCK
VALUE
Res.
Res.
rs
r
15
14
13
POLA
Res.
Res.
Res.
RITY
rw
Bit 31 LOCK: locks the whole content of the register, COMP1_CSR[31:0]
Bit 30 VALUE: COMP1 output status bit
Bits 29:27 Reserved, must be kept at reset value.
Bits 26:25 INMESEL[1:0]: COMP1 input minus extended selection
Bit 24 Reserved, must be kept at reset value.
Bit 23 SCALEN: voltage scaler enable
Bit 22 BRGEN: scaler bridge enable
Bit 21 Reserved, must be kept at reset value.
28
27
26
25
Res.
INMESEL[1:0]
rw
rw
12
11
10
9
Res.
Res.
Res.
This bit is set by software and cleared by a hardware system reset.
0: COMP1_CSR[31:0] are read/write.
1: COMP1_CSR[31:0] are read-only.
This bit is read-only. It reflects the current COMP1 output taking into account the effect of the
POLARITY bit.
These bits are set and cleared by software. They select which extended GPIO input is
connected to the input minus of COMP1, if INMSEL[2:0] = 111.
00: PA10
01: PA11
10: PA15
11: reserved
This bit is set and cleared by software. It enables outputs of the V
the minus input of COMP1.
0: Bandgap scaler disabled (if SCALEN bit of COMP2_CSR register is also reset)
1: Bandgap scaler enabled
This bit is set and cleared by software. It enables the bridge of the scaler.
If SCALEN is set and BRGEN is reset, the BG voltage reference is available but not 1/4
BGAP, 1/2 BGAP or 3/4 BGAP. The BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4
BGAP. If SCALEN and BRGEN are both set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP
voltage references are available.
0: Scaler resistor bridge disabled (if BRGEN bit of COMP2_CSR register is also reset)
1: Scaler resistor bridge enabled
24
23
22
SCAL
Res.
BRGEN
EN
rw
rw
8
7
6
INPSEL[1:0]
INMSEL[2:0]
rw
rw
rw
RM0461 Rev 5
Comparator (COMP)
21
20
19
18
Res.
BLANKING[2:0]
rw
rw
rw
5
4
3
2
PWRMODE[1:0]
rw
rw
rw
rw
divider available on
REFINT
17
16
HYST[1:0]
rw
rw
1
0
Res.
EN
rw
523/1306
527
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