STMicroelectronics STM32WLEx Reference Manual page 309

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0461
8
General-purpose I/Os (GPIO)
8.1
GPIO introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and one 32-bit set/reset register (GPIOx_BSRR).
All GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
8.2
GPIO main features
Output states: push-pull or open drain + pull-up/down
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
Speed selection for each I/O
Input states: floating, pull-up/down, analog
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
Analog function
Alternate function selection registers
Fast toggle capable of changing every two clock cycles
Highly flexible pin multiplexing allowing the use of I/O pins as GPIOs or as one of
several peripheral functions
8.3
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of GPIO ports can be individually configured by software in several modes listed
below:
Input floating
Input pull-up
Input pull-down
Analog
Output open-drain with pull-up or pull-down capability
Output push-pull with pull-up or pull-down capability
Alternate function push-pull with pull-up or pull-down capability
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers must be accessed
as 32-bit words, half-words or bytes.
RM0461 Rev 5
General-purpose I/Os (GPIO)
309/1306
340

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