STMicroelectronics STM32WLEx Reference Manual page 412

Extended interrupts and event controller (EXTI)
Bit 16 FT16: falling trigger event configuration bit of configurable event input 16
Bit 15 FT15: falling trigger event configuration bit of configurable event input 15
Bit 14 FT14: falling trigger event configuration bit of configurable event input 14
Bit 13 FT13: falling trigger event configuration bit of configurable event input 13
Bit 12 FT12: falling trigger event configuration bit of configurable event input 12
Bit 11 FT11: falling trigger event configuration bit of configurable event input 11
Bit 10 FT10: falling trigger event configuration bit of configurable event input 10
Bit 9 FT9: falling trigger event configuration bit of configurable event input 9
Bit 8 FT8: falling trigger event configuration bit of configurable event input 8
Bit 7 FT7: falling trigger event configuration bit of configurable event input 7
Bit 6 FT6: falling trigger event configuration bit of configurable event input 6
Bit 5 FT5: falling trigger event configuration bit of configurable event input 5
Bit 4 FT4: falling trigger event configuration bit of configurable event input 4
Bit 3 FT3: falling trigger event configuration bit of configurable event input 3
Bit 2 FT2: falling trigger event configuration bit of configurable event input 2
Bit 1 FT1: falling trigger event configuration bit of configurable event input 1
Bit 0 FT0: falling trigger event configuration bit of configurable event input 0
14.6.3 EXTI software interrupt event register (EXTI_SWIER1)
Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
SWI15 SWI14 SWI13 SWI12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SWI22: Software interrupt on line 22
Bit 21 SWI21: Software interrupt on line 21
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 SWI16: Software interrupt on line 16
412/1306
28 27 26 25
Res. Res. Res.
12 11 10 9
SWI11 SWI10 SWI9
rw rw rw rw
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 22.
This bit is automatically cleared by hardware.
24 23 22
Res. Res. SWI22 SWI21
rw
8 7 6
SWI8 SWI7 SWI6 SWI5
rw rw rw
RM0461 Rev 5
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
SWI4 SWI3 SWI2
rw rw rw rw
RM0461
17 16
Res. SWI16
rw
1 0
SWI1 SWI0
rw rw