STMicroelectronics STM32WLEx Reference Manual page 93

RM0461
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 EMPTY: Flash user area empty
Bit 15 PES: CPU program/erase suspend request
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 DCRST: CPU data cache reset
Bit 11 ICRST: CPU instruction cache reset
Bit 10 DCEN: CPU data cache enable
Bit 9 ICEN: CPU instruction cache enable
Bit 8 PRFTEN: CPU prefetch enable
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LATENCY[2:0]: Latency
When read, this bit indicates whether the first location of the user flash is erased or has a
programmed value.
0: Read: user flash programmed
1: Read: user flash empty
0: Flash program and erase operations granted
1: Any new flash program and erase operation is suspended until this bit is cleared. The
PESD bit in FLASH_SR is set when PES bit in FLASH_ACRis set.
0: CPU data cache not reset
1: CPU data cache reset
This bit can be written only when the data cache is disabled.
0: CPU instruction cache not reset
1: CPU instruction cache reset
This bit can be written only when the instruction cache is disabled.
0: CPU data cache disabled
1: CPU data cache enabled
0: CPU instruction cache disabled
1: CPU instruction cache enabled
0: CPU prefetch disabled
1: CPU prefetch enabled
These bits represent the ratio of the flash HCLK clock period to the flash memory access
time.
000: Zero wait state
001: One wait state
010: Two wait states
Others: reserved
RM0461 Rev 5
Embedded flash memory (FLASH)
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