Exti Pending Register (Exti_Pr2); Exti Interrupt Mask Register (Exti_Imr1) - STMicroelectronics STM32WLEx Reference Manual

Extended interrupts and event controller (EXTI)
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 SWI45: software interrupt on event 45
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 SWI34: software interrupt on event 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.8

EXTI pending register (EXTI_PR2)

Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. PIF45 Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
14.6.9

EXTI interrupt mask register (EXTI_IMR1)

Address offset: 0x080
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
416/1306
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 45.
This bit is automatically cleared by hardware.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
IM[31:16]
rw rw rw
8 7 6
IM[15:0]
rw rw rw
RM0461 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. PIF34
rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0461
17 16
Res. Res.
1 0
Res. Res.
17 16
rw rw
1 0
rw rw