Independent Analog Peripherals Supply; Battery Backup Domain - STMicroelectronics STM32WLEx Reference Manual

RM0461
The inrush current of the LDO and SMPS step-down converter can be controlled via the
sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz
radio Deep-Sleep mode. For more details see
The SMPS needs a clock to be functional. If for any reason this clock stops, the device may
be destroyed. It can be the case if the HSE is provided by an external clock source
(Figure 22: HSE32 clock
enabled. To avoid this situation, a clock detection is used to, in case of a clock failure, switch
off the SMPS and enable the LDO. The SMPS clock detection is enabled by the sub-GHz
radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled and
must be enabled before enabling the SMPS. For more details, see
radio (SUBGHZ).
5.1.1

Independent analog peripherals supply

To improve the ADC conversion accuracy and to extend the supply flexibility, the analog
peripherals have an independent power supply that can be separately filtered and shielded
from noise on the PCB.
The analog peripherals voltage supply input is available on a separate VDDA pin.
An isolated supply ground connection is provided on VSSA pin.
The V
DDA
before enabling any of the analog peripherals supplied by V
comparators, voltage reference buffer).
The V
DDA
a threshold (1.65 V for PVM3). See
more details.
When a single supply is used, V
external filtering circuit in order to ensure a noise-free V
ADC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a
separate reference voltage lower than V
represented by the full scale value, for an analog input (ADC) signal.
V can be provided either by an external reference of by an internal buffered voltage
REF+
reference (VREFBUF).
The internal voltage reference is enabled by setting the ENVR bit in the
and status register
bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also
provide the voltage to external components through V
datasheet and to
5.1.2

Battery Backup domain

To retain the content of the backup registers and supply the RTC and TAMP functions when
V is turned off, the VBAT pin can be connected to an optional backup voltage supplied by
DD
a battery or by another source.
sources), with the risk that this clock disappears while the SMPS is
supply voltage can be different from V
supply can be monitored by the peripheral voltage monitoring, and compared with
(VREFBUF_CSR). The voltage reference is set to 2.5 V when the VRS
Voltage reference buffer (VREFBUF)
Section 4: Sub-GHz radio
. The presence of V
DD
Section 5.2.3: Peripheral voltage monitoring (PVM)
can be externally connected to V
DDA
, to V
DDA REF+
RM0461 Rev 5
Power control (PWR)
(SUBGHZ).
Section 4: Sub-GHz
must be checked
DDA
(A/D converter,
DDA
through the
DD
reference voltage.
DDA
. V is the highest voltage,
REF+
VREFBUF control
pin. Refer to the device
REF+
for further information.
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