Table 99. Dac Features; Figure 72. Dac Block Diagram - STMicroelectronics STM32WLEx Reference Manual

Digital-to-analog converter (DAC)
17.3 DAC implementation
Dual channel
Output buffer
I/O connection
Maximum sampling time
Autonomous mode
VREF+ pin
17.4 DAC functional description
17.4.1 DAC block diagram
dac_ch1_trg1
dac_ch1_trg15
dac_ch1_dma
dac_unr_it
dac_pclk
dac_hold_ck
1. MODE1 bits in the DAC_MCR control the output mode and the switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
488/1306

Table 99. DAC features

DAC features

Figure 72. DAC block diagram

Offset
calibration
OTRIM1[5:0]
bits
TRIG
MODE1 bits
TSEL1
DOR1
[3:0]
bits
Control registers
and logic
channel1
RM0461 Rev 5
DAC_OUT1 to PA10
V
DD
DAC
converter
12-bit
Sample and hold
registers
TSAMPLE1
THOLD1
TREFRESH1
V
SS
RM0461
DAC
-
X
1 Msps
-
X
Buffer
dac_out1
MSv61355V5