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Reset and clock control (RCC)
6.4.8
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x028
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Bits 11:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1RST: DMAMUX1 reset
Bit 1 DMA2RST: DMA2 reset
Bit 0 DMA1RST: DMA1 reset
6.4.9
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x02C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
264/1306
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
CRC
Res.
Res.
Res.
RST
rw
This bit is set and cleared by software.
0: No effect
1: CRC reset
This bit is set and cleared by software.
0: No effect
1: DMAMUX1 reset
This bit is set and cleared by software.
0: No effect
1: DMA2 reset
This bit is set and cleared by software.
0: No effect
1: DMA1 reset
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
GPIOH
Res.
Res.
RST
rw
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
DMA
Res.
Res.
Res.
MUX1
RST
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
GPIOC
Res.
Res.
Res.
RST
rw
RM0461
17
16
Res.
Res.
1
0
DMA2
DMA1
RST
RST
rw
rw
17
16
Res.
Res.
1
0
GPIOB
GPIOA
RST
RST
rw
rw
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