Hsi16 Clock; Figure 23. Hse32 Tcxo Control - STMicroelectronics STM32WLEx Reference Manual

RM0461
The control of the HSE32 external TCXO can be done in the following ways:
• powered by V
–
–
–
–
When the CPUis in one of the low-power modes (Stop, Standby, or Shutdown) and the sub-
GHz radio is in Sleep, the HSE32 clock including the TCXO is disabled.
6.2.2

HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz Oscillator.
The HSI16 oscillator has the advantage of providing a clock source at low cost. It also has a
faster startup time than the HSE32 crystal oscillator however, even with calibration the
frequency is less accurate than an external crystal oscillator or ceramic resonator.
The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop 0,
Stop 1 or Stop 2). Refer to
clock source (auxiliary clock) if the HSE32 crystal oscillator fails. Refer to
Clock security system on HSE32
Calibration
The RC oscillator frequencies can vary from one chip to another due to manufacturing
process variations. This is why each device is factory calibrated by ST for 1 % accuracy at
T = 25 °C.
A
After a reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
internal clock sources calibration register

Figure 23. HSE32 TCXO control

PB0 GPIO
HSEBYPPWR
tcxoon
HSEON
oscon
OSC
Radio control
Control
HSERDY
RDY
HSEclk
Control
:
DDTCXO
Set the voltage level inside the sub-GHz radio by using the Set_TcxoMode()
command, before enabling the VDDTCXO regulator.
Set the HSEBYPPWR bit to 1 to use the VDDTCXO regulator.
Enable the HSE32 use with external TCXO in Run mode for the CPU with the
HSEON bit.The availability of the clock can be checked with the HSERDY bit.
Enable the HSE32 use with TXCXO for the sub-GHz radio with the sub-GHz radio
Set_TcxoMode() command when in sub-GHz radio Standby mode. It is
recommended to issue a sub-GHz radio calibration command once the HSE32
clock is available.
Section 6.3: Low-power
LDO
1
TCXO
0
OSC
HSE32
en
C
LIN
clk
modes. It can also be used as a backup
(CSS).
(RCC_ICSCR).
RM0461 Rev 5
Reset and clock control (RCC)
VDDRF
PB0-VDDTCXO
VDD TCXO
TCXO
OSC_IN
R CLK
OSC_OUT NC
Note: Force SUBGHZ_HSEINTRIMR = 0x00
to get C = 11.3 pF.
LIN
Section 6.2.10:
MSv62607V2
RCC
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