STMicroelectronics STM32WLEx Reference Manual page 391

RM0461
12.4.6 DMAMUX request generator
The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.
Note: The GNBREQ field value must be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
There is no hardware write protection.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.
Trigger overrun and interrupt
If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the status
DMAMUX_RGSR register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the
completion of the usage of the related channel of the DMA controller. Else, upon a new
detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that
is, no served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.
DMA request multiplexer (DMAMUX)
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