Figure 123. Counter Timing Diagram, Internal Clock Divided By 1; Figure 124. Counter Timing Diagram, Internal Clock Divided By 2 - STMicroelectronics STM32WLEx Reference Manual

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
628/1306

Figure 123. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
05
(UIF)

Figure 124. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0002
(UIF)
RM0461 Rev 5
04
03 02 01 00 36
0001 0000
35 34 33 32
31
0036 0034
0035
RM0461
30 2F
MS31184V1
0033
MS31185V1