STMicroelectronics STM32WLEx Reference Manual page 73

RM0461 Embedded flash memory (FLASH)
performance advantage of the Cortex-M4 with DSP over flash memory technologies, which
normally require the processor to wait for the flash memory at higher operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache that increases program execution speed from the 64-bit
®
flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART Accelerator is equivalent to 0 wait state program execution from the flash memory at a
CPU frequency up to 48 MHz.
Instruction prefetch
The CPU fetches the instruction over the ICode bus and the literal pool (constant/data) over
the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses.
Each flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bit current instruction
line is saved in a current buffer. In case of sequential code, at least two CPU cycles are
needed to execute the previous read instruction line. Prefetch on the CPU ICode bus can
be used to read the next sequential instruction line from the flash memory while the current
instruction line is being requested by the CPU.
Prefetch is enabled by setting PRFTEN in FLASH_ACR. This feature is useful if at least one
wait state is needed to access the flash memory.
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