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RM0461
Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: USART1 bus clock disabled by the clock gating during Sleep and Stop modes
1: USART1 bus clock enabled by the clock gating during Sleep mode, disabled during Stop
mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: SPI1 clock disabled by the clock gating during Sleep and Stop modes
1: SPI1 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 11 TIM1SMEN: Timer 1 clock enable during Sleep and Stop modes
This bit is set and cleared by software.
0: TIM1 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM1 clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clocks enable during Sleep and Stop modes
This bit is set and cleared by software.
0: ADC bus clock disabled by the clock gating during Sleep and Stop modes
1: ADC bus clock enabled by the clock gating during Sleep mode, disabled during Stop mode
Bits 8:0 Reserved, must be kept at reset value.
6.4.28
RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR)
Address offset: 0x084
Reset value: 0x0000 0001
Access: word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPISMEN: Sub-GHz radio SPI clock enable during Sleep and Stop modes
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disabled by the clock gating during Sleep and Stop modes
1: Sub-GHz radio SPI clock enabled by the clock gating during Sleep mode, disabled during
Stop mode
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
rw
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