STMicroelectronics STM32WLEx Reference Manual page 49

RM0461 List of figures
Figure 101. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 102. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 103. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Figure 104. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 105. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Figure 106. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 107. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 108. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 109. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Figure 110. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Figure 111. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 577
Figure 112. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 578
Figure 113. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 114. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Figure 115. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 622
Figure 116. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 622
Figure 117. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 118. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Figure 119. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 120. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 121. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 626
Figure 122. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 626
Figure 123. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Figure 124. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Figure 125. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 126. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Figure 127. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 630
Figure 128. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 631
Figure 129. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 130. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 632
Figure 131. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 132. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 633
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 634
Figure 134. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 635
Figure 135. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Figure 136. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Figure 137. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 637
Figure 138. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 139. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Figure 140. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Figure 141. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 142. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 641
Figure 143. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 144. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 642
Figure 145. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 146. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 643
Figure 147. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Figure 148. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Figure 149. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
Figure 150. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
Figure 151. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 651
Figure 152. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
RM0461 Rev 5 49/1306
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