STMicroelectronics STM32WLEx Reference Manual page 324

General-purpose I/Os (GPIO)
8.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B)
Address offset: Block A: 0x0028
Address offset: Block B: 0x0428
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
BR15 BR14 BR13 BR12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BRy: Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
8.4.12 GPIOC mode register (GPIOC_MODER)
Address offset: 0x0800
Reset value: 0xFC00 3FFF
31 30 29 28
MODE15[1:0] MODE14[1:0]
rw rw rw rw
15 14 13 12
Res. Res. MODE6[1:0]
rw rw
Bits 31:30 MODE15[1:0]: Port PC15 IO type configuration
Bits 29:28 MODE14[1:0]: Port PC14 IO type configuration
Bits 27:26 MODE13[1:0]: Port PC13 IO type configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 MODE6[1:0]: Port PC6 IO type configuration
Bits 11:10 MODE5[1:0]: Port PC5 IO type configuration
Bits 9:8 MODE4[1:0]: Port PC4 IO type configuration
Bits 7:6 MODE3[1:0]: Port PC3 IO type configuration
324/1306
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
BR11 BR10 BR9
rc_w1 rc_w1 rc_w1
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Resets the corresponding GPIOx_ODR.OD[y] bit.
27 26 25
MODE13[1:0] Res.
rw rw
11 10 9
MODE5[1:0] MODE4[1:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
BR8 BR7 BR6
rc_w1 rc_w1 rc_w1
24 23 22
Res. Res. Res. Res.
8 7 6
MODE3[1:0]
rw rw rw
RM0461 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
BR5 BR4 BR3 BR2
rc_w1 rc_w1 rc_w1 rc_w1
21 20 19 18
Res. Res. Res.
5 4 3 2
MODE2[1:0] MODE1[1:0]
rw rw rw rw
RM0461
17 16
Res. Res.
1 0
BR1 BR0
rc_w1 rc_w1
17 16
Res. Res.
1 0
MODE0[1:0]
rw rw