Figure 106. Message Construction In Gmac Mode; Figure 107. Gmac Authentication Mode - STMicroelectronics STM32WLEx Reference Manual

AES hardware accelerator (AES)
A typical message construction for GMAC is given in
AES GMAC processing
Figure 107
selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.
Legend
The GMAC algorithm corresponds to the GCM algorithm applied on a message only
containing a header. As a consequence, all steps and settings are the same as with the
GCM, except that the payload phase is omitted.
568/1306

Figure 106. Message construction in GMAC mode

16-byte
boundaries
ICB
4-byte boundaries
Initialization vector (IV)
Zero padding
describes the GMAC mode implementation in the AES peripheral. This mode is

Figure 107. GMAC authentication mode

(1) Init
AES_KEYRx (KEY)
(2) Header
AES_DINR
(message block 1)
Swap
management DATATYPE
[1:0]
GF2mul
H H
input
output
XOR
Len(A)
Authenticated data
Authentication tag (T)
Counter
(4) Final
[0]
128
Encrypt
AES_KEYRx (KEY)
H
AES_DINR
(message block n)
Swap
management
GF2mul
RM0461 Rev 5
Figure 106.
[Len(A)]
0
AES_IVRx
IV + 32-bit counter (= 0x0)
Encrypt
AES_DINR
len(A) || [0]
64 64
GF2mul
H
S
AES_DOUTR
(authentication tag T)
RM0461
[0]
64 64
Last
block
MSv42158V2
MSv42150V2