Enter Low-Power Mode; Exit Low-Power Mode; Table 39. Lprun - STMicroelectronics STM32WLEx Reference Manual

Power control (PWR)
Enter LPRun mode
To enter the LPRun mode, proceed as follows (refer to
1. Jump into the SRAM and power down the flash memory by setting the FPDR bit in the
Section 5.5.1: PWR control register 1 (PWR_CR1)
2. Disable HSE32 clock.
3. Decrease the HCLK clock frequencies below 2 MHz.
4. Force the regulator in low-power mode by setting the LPR bit in the
register 1
Exit LPRun mode
To exit the LPRun mode, proceed as follows (refer to
1. Force the regulator in main mode by clearing the LPR bit in the
(PWR_CR1).
2. Wait until REGLPF bit is cleared in the
3. Increase the HCLK clock frequency (enable HSE32 clock when needed).
LPRun mode
Mode entry
Mode exit
Wakeup latency
5.4.3

Enter low-power mode

The MCU enters low-power mode following one of these events:
• when MCU executes the WFI (wait for interrupt)
•
when MCU executes WFE (wait for event) instructions
• on return from ISR when the SLEEPONEXIT bit in the CPU system control register is
set
Low-power mode is only be entered if no interrupt or event is pending.
5.4.4

Exit low-power mode

From Sleep and Stop modes, the CPU exits low-power mode depending on the way the
mode was entered, as detailed below:
•
If the WFI instruction or return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the CPU exits the
low-power mode as soon as an event occurs. The wakeup event can be generated
either by an NVIC IRQ interrupt or by an event.
–
200/1306
(PWR_CR1).
Decrease the system clock frequency below 2 MHz. LPR = 1.
LPR = 0. Wait until REGLPF = 0. Increase the system clock frequency.
Regulator wakeup time from low-power mode
Wakeup generated by an NVIC IRQ with SEVONPEND = 0 in the CPU system
control register, enabling an interrupt in the peripheral control register and
in the NVIC)
When the CPU resumes from WFE, the peripheral interrupt pending bit and the
NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
Table
Power status register 2

Table 39. LPRun

Description
RM0461 Rev 5
Table 39):
(optional).
PWR control
39):
PWR control register 1
(PWR_SR2).
RM0461