Figure 183. Counter Timing Diagram, Internal Clock Divided By 1; Figure 184. Counter Timing Diagram, Internal Clock Divided By 2 - STMicroelectronics STM32WLEx Reference Manual

RM0461
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 183. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
05
(UIF)

Figure 184. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0002
(UIF)
RM0461 Rev 5
04
02 01 00 36
03
0000
0001
General-purpose timer (TIM2)
35 34 33 32
31
0036 0035 0034
30 2F
MS31184V1
0033
MS31185V1
727/1306
789