RM0461
DMA request multiplexer (DMAMUX)
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.
RM0461 Rev 5
397/1306
399
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