STMicroelectronics STM32WLEx Reference Manual page 895

RM0461
When the binary mode is used, the subsecond field can be programmed in the alarm binary
register RTC_ALRMABINR.
The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.
Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous
prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct
behavior.
Alarm A and alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
TAMPALRM output. TAMPALRM output polarity can be configured through bit POL the
RTC_CR register.
30.3.8 Periodic auto-wakeup
The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input ck_wut can be:
•
RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE (32.768 kHz), this allows the wakeup interrupt period to be
configured from 122 µs to 32 s, with a resolution down to 61 µs.
•
ck_spre (usually 1 Hz internal clock) in BCD mode, or the clock used to update the
calendar as defined by BCDU in binary or mixed (BCD-binary) modes.
When ck_spre frequency is 1 Hz, this allows a wakeup time to be achieved from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
–
–
Depending on WUTOCLR in the RTC_WUTR register, the WUTF flag must either be
cleared by software (WUTOCLR = 0x0000), or the WUTF is automatically cleared by
hardware when the auto-reload down counter reaches WUTOCLR value
(0x0000<WUTOCLR<=WUT).
The wakeup flag is output on an internal signal rtc_wut that can be used by other
peripherals (refer to section
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR
register, it can exit the device from low-power modes.
The periodic wakeup flag can be routed to the TAMPALRM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. TAMPALRM output polarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on
the wakeup timer.
from 1 s to 18 hours when WUCKSEL [2:1] = 10
and from around 18 h to 36 h when WUCKSEL[2:1] = 11. In this last case 2
added to the 16-bit counter current value. When the initialization sequence is
complete (see Programming the wakeup timer on page
counting down. When the wakeup function is enabled, the down-counting remains
active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in
the RTC_SR register, and the wakeup counter is automatically reloaded with its
reload value (RTC_WUTR register value).
Section 30.3.1: RTC block
RM0461 Rev 5
Real-time clock (RTC)
898), the timer starts
diagram).
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