STMicroelectronics STM32WLEx Reference Manual page 78

Embedded flash memory (FLASH)
It is only possible to program a double-word (2 x 32-bit data), otherwise:
•
Any attempt to write a byte (8 bits) or half-word (16 bits) sets SIZERR in FLASH_SR.
•
Any attempt to write a double-word that is not aligned with a double-word address sets
the PGAERR flag in FLASH_SR.
Standard programming
The flash memory programming sequence in standard mode is as follows:
1. Check that no flash main memory operation is ongoing by checking BSY in
FLASH_SR.
2. Check that flash program and erase operation is allowed by checking PESD in
FLASH_SR.
3. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
4. Set PG in FLASH_CR.
5. Perform the data write operation at the desired memory address, inside the main
memory block or OTP area. Only double-word (64 bits) can be programmed.
a)
b)
Note: When the flash memory interface received a good sequence (a double-word),
programming is automatically launched and the BSY bit is set. The internal oscillator
HSI16 (16 MHz) is enabled automatically when the PG bit is set, and disabled
automatically when the PG bit is cleared, except if the HSI16 is previously enabled
with HSION in the RCC_CR register.
If the user needs to program only one word, double-word must be completed with the
erase value 0xFFFF FFFF to launch automatically the programming.
ECC is calculated from the double-word to program.
For correct operation, the firmware must guarantee that the flash page access
protection is not changed during the programming sequence. This is between the first
and second word write.
6. Wait until BSY is cleared in FLASH_SR.
7. Check that EOP is set in FLASH_SR (meaning the programming operation
succeeded), and clear it by software.
8. Clear PG in FLASH_SR if there no more programming request.
Fast programming
This mode allows a row to be programmed, 32 double-words (256 bytes), and the page
programming time to be reduced by eliminating the need for verifying the flash memory
locations before they are programmed and to avoid rising and falling time of high voltage for
each double-word. During fast programming, the flash clock frequency (HCLK3) must be at
least 8 MHz.
Fast row programming must be performed by executing firmware from SRAM and disabling
interrupts when not relocating the CPU interrupt vector table. A read access form the CPU
requesting row programming causes a bus error. A read from any other source (such as the
DMA) is stalled until the row programming is finished (standard double-word programming
does not cause a bus error to the requesting CPU but stalls any read until standard
programming is finished).
78/1306
Write a first word in an address aligned with double-word
Write the second word (see the note below)
RM0461 Rev 5
RM0461