Table 210. Stm32Wlex I2C Implementation - STMicroelectronics STM32WLEx Reference Manual

Inter-integrated circuit (I2C) interface
•
Wakeup from Stop mode on address match.
32.3 I2C implementation
The devices incorporate up to three I²C-bus controllers, I2C1, I2C2, and I2C3, with full or
limited feature sets as shown in the following table.
7-bit addressing mode
10-bit addressing mode
Standard-mode (up to 100 kbit/s)
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Independent clock
Wakeup from Stop mode
SMBus/PMBus
1. X = supported.
2. The register content is lost in Stop 2 mode.
3. Wakeup supported from Stop 0 and Stop 1 modes.
4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
32.4 I2C functional description
In addition to receiving and transmitting data, this interface converts them from serial to
parallel format and vice versa. The interrupts are enabled or disabled by software. The
interface is connected to the I
connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus
(up to 1 MHz) I
This interface can also be connected to an SMBus with the data pin (SDA) and clock pin
(SCL).
If SMBus feature is supported, the additional optional SMBus Alert pin (SMBA) is also
available.
948/1306

Table 210. STM32WLEx I2C implementation

(1)
I2C features
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be
2
C bus.
RM0461 Rev 5
(2) (2)
I2C1 I2C2
X X
X X
X X
X X
X X
X X
(3) (3)
X X
X X
RM0461
I2C3
X
X
X
X
X
X
(4)
X
X