Table 70. Dma Register Map And Reset Values - STMicroelectronics STM32WLEx Reference Manual

RM0461
Bits 31:0 PA[31:0]: peripheral address
It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: This register is set and cleared by software (privileged software if the channel is in
11.6.6 DMA channel x memory address register (DMA_CMARx)
Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 MA[31:0]: peripheral address
It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: This register is set and cleared by software (privileged software if the channel is in
11.6.7 DMA register map
Offset Register
DMA_ISR
0x000
Reset value
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
27 26 25
rw rw rw
11 10 9
rw rw rw
privileged mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

Table 70. DMA register map and reset values

0 0 0 0 0 0
RM0461 Rev 5
Direct memory access controller (DMA)
24 23 22 21
MA[31:16]
rw rw rw rw
8 7 6 5
MA[15:0]
rw rw rw rw
0 0 0 0 0 0 0 0
20 19 18
rw rw rw
4 3 2
rw rw rw
0 0 0 0 0 0 0 0 0
17 16
rw rw
1 0
rw rw
0 0 0 0 0
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