Table 54. Low-Power Debug Configurations - STMicroelectronics STM32WLEx Reference Manual

RM0461
by the peripheral (USART1, USART2, LPUART1, I2C1, I2C2 or I2C3) that allows the
wakeup from Stop modes.
All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even
when the MCU is in Stop mode (if HSI16 is selected as clock source for that peripheral).
All U(S)ARTs, LPUARTs and LPTIMs can also be driven by the LSE oscillator when the
system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case, LSE remains always on in Stop mode (no
capability to turn on the LSE oscillator).
All LPTIMs can also be driven by the LSI oscillator when the system is in Stop mode (if LSI
is selected as clock source for that peripheral) and the LSI oscillator is enabled (LSION).
Standby and Shutdown modes stop all clocks in the V
HSI16, the MSI and the HSE32 oscillators.
The low-power modes can be overridden for debugging the CPU by setting the
DBG_SLEEP, DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. In
addition, the EXTI CDBGPWRUPREQ events can be used to allow debugging the CPU in
Stop modes (see the table below).
Mode
Sleep
Stop 0
and
Stop 1
Stop 0,
Stop 1
and
Stop 2
Standby
1. x = Don't care.
When leaving the Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or
HSI16, depending on the software configuration of the STOPWUCK bit in the
configuration register
oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If
the MSI was in PLL-mode before entering Stop mode, the PLL-mode stabilization time must
be waited for after wakeup, even if LSE was kept on during the Stop mode.
When exiting Standby mode, the system clock is MSI at 4 MHz.
When exiting Shutdown modes, the system clock is MSI. The MSI frequency at wakeup
from Shutdown mode is 4 MHz. The user trim is lost.
If a Flash memory programming operation is ongoing, Stop, Standby and Shutdown modes
entry is delayed until the Flash memory interface access is finished. If an access to the APB

Table 54. Low-power debug configurations

CDBGPWRUPREQ
CPU DBG_STANDBY
(1)
x
Disabled
Enabled
x
x
(RCC_CFGR). The frequency (range and user trim) of the MSI
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CORE
DBGMCU
DBG_STOP
x x
Disabled
x
Enabled
Disabled
x
Enabled
Reset and clock control (RCC)
domain and disable the PLL, the
DBG_SLEEP
x
x
x
RCC clock
Debug
CPU
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
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