STMicroelectronics STM32WLEx Reference Manual page 52

List of figures RM0461
Figure 252. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 850
Figure 253. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
Figure 254. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
Figure 255. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Figure 256. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . . 871
Figure 257. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
Figure 258. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 259. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Figure 260. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
Figure 261. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
Figure 262. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Figure 263. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Figure 264. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Figure 265. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 266. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 267. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 268. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Figure 269. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . . 963
Figure 270. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . . 964
Figure 271. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Figure 272. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 966
Figure 273. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 967
Figure 274. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Figure 275. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Figure 276. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Figure 277. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Figure 278. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Figure 279. Transfer sequence flow for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . . . . . 973
Figure 280. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . . . . . . . . . . . . . 974
Figure 281. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 282. Transfer sequence flow for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . . . . . . 977
Figure 283. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . . . . . 978
Figure 284. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
Figure 285. Timeout intervals for t , t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
LOW:SEXT LOW:MEXT
Figure 286. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . . 987
Figure 287. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 987
Figure 288. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . . . . . 989
Figure 289. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 990
Figure 290. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Figure 291. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Figure 292. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Figure 293. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
Figure 294. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Figure 295. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Figure 296. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Figure 297. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Figure 298. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Figure 299. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Figure 300. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Figure 301. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Figure 302. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1043
52/1306 RM0461 Rev 5