Sleep Mode; Table 40. Cpu Wakeup Versus System Operating Mode - STMicroelectronics STM32WLEx Reference Manual

RM0461
–
–
From Standby and Shutdown modes, the CPU exits low-power mode through an external
reset (NRST pin), an IWDG reset, a sub-GHz radio IRQ, a PVD event, an edge on the sub-
GHz radio busy signal, a edge on one of the enabled WKUPx pins, an RTC and TAMP
event, or a radio event (for Standby only).
After waking up from Standby or Shutdown mode, the program execution restarts in the
same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched).
The system mode when it wakes up from low-power mode can be determined from the
C1STOPF, C1STOP2F and C1SBF bits in the
register (PWR_EXTSCR).
System
mode
Run
Stop
Standby
N/A
5.4.5

Sleep mode

I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Enter Sleep mode
The Sleep mode is entered from Run mode according to
SLEEPDEEP bit in the CPU system control register is cleared (see
register) must be cleared. Only NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
Wakeup generated by an NVIC IRQ with SEVONPEND = 1 in the CPU system
control register, enabling an interrupt in the peripheral control register and
optionally in the NVIC
When the CPU resumes from WFE, the peripheral interrupt pending bit and when
enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) must be cleared. All NVIC interrupts wake up the CPU, even the
disabled ones. Only enabled NVIC interrupts with sufficient priority wake up and
interrupt the CPU.
Wakeup generated by an event, configuring an EXTI line in event mode
When the CPU resumes from WFE, it is not necessary to clear the EXTI
peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the
pending bits corresponding to the event line is not set. It may be necessary to
clear the interrupt flag in the peripheral.

Table 40. CPU wakeup versus system operating mode

CPU
0 0 0 Kept running
0 1 0 Wakeup from Stop 0 or 1
0 0 1 Wakeup from Stop 2
1 0 0 Wakeup from Standby
Others Not valid, does not occur
PWR extended status and status clear
CPU wakeup
RM0461 Rev 5
Power control (PWR)
Enter low-power mode, when the
Table 41).
201/1306
229