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RM0461
9.2.10
SYSCFG SRAM2 key register (SYSCFG_SKR)
Address offset: 0x024
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_SCSR register.
1. Write 0xCA into Key[7:0].
2. Write 0x53 into Key[7:0].
Writing a wrong key reactivates the write protection.
9.2.11
SYSCFG radio debug control register (SYSCFG_RFDCR)
Address offset: 0x208
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 RFTBSEL: radio debug test bus selection
0 Digital test bus selected on RF_ADTB[3:0]
1: Analog test bus selected on RF_ADTB[3:0]
9.2.12
SYSCFG register map
Offset Register name
SYSCFG_
MEMRMP
0x000
Reset value
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Table 64. SYSCFG register map and reset values
System configuration controller (SYSCFG)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
w
w
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
KEY[7:0]
w
w
w
w
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
w
w
17
16
Res.
Res.
1
0
RFTBS
Res.
EL
rw
x
x
x
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