Flash Program And Erase Operations - STMicroelectronics STM32WLEx Reference Manual

RM0461
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.
CPU instruction cache memory (I-Cache)
To limit the CPU time lost due to jumps, it is possible to retain 32 lines of 4 x 64 bits
(1 Kbyte) in an instruction cache memory.This feature is enabled for the CPU by setting the
instruction cache enable (ICEN) bit in FLASH_ACR. Each time a miss occurs (requested
data not present in the currently used instruction line, in the prefetched instruction line or in
the instruction cache memory), the line read is copied into the instruction cache memory. If
some data contained in the instruction cache memory are requested by the CPU, they are
provided without inserting any delay. Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to determine the line to replace in the
instruction memory cache. This feature is particularly useful in case of code containing
loops.
The instruction cache memory is enabled after system reset.
CPU data cache memory (D-Cache)
CPU literal pools are fetched from the flash memory through the DCode bus during the
execution stage of the CPU pipeline. Each CPU DCode bus read access fetches 64 bits that
are saved in a current buffer. The CPU pipeline is consequently stalled until the requested
literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB
data bus DCode have priority over accesses through the AHB instruction bus ICode.
If some literal pools are frequently used, the CPU data cache memory can be enabled by
setting the data cache enable (DCEN) bit in FLASH_ACR. This feature works like the
instruction cache memory but the retained data size is limited to eight lines of 4 x 64 bits
(256 bytes).
The data cache memory is enabled after system reset.
Note: The D-Cache is active only when data is requested by the CPU (not by DMAs).
Data in option bytes block are not cacheable.
3.3.6

Flash program and erase operations

The embedded flash memory can be programmed using in-circuit programming or in-
application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the flash
memory using the JTAG, SWD protocol or the supported interfaces by the system
bootloader, to load the user application for the CPU, into the microcontroller. ICP offers
quick and efficient design iterations and eliminates unnecessary package handling or
socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (such as I/Os, UART, I
to download programming data into memory. IAP allows the user to re-program the flash
memory while the application is running. Nevertheless, part of the application must have
been previously programmed in the flash memory using ICP.
RM0461 Rev 5
Embedded flash memory (FLASH)
2
C or SPI)
75/1306
108