S0: Cpu I-Bus; S1: Cpu D-Bus; S2: Cpu S-Bus; Figure 1. System Architecture - STMicroelectronics STM32WLEx Reference Manual

Memory and bus architecture
This architecture is shown in the figure below.
CPU
Arm
Cortex-M4
S0 S1 S2
2.1.1

S0: CPU I-bus

This bus connects the instruction bus of the CPU core to the bus matrix. This bus is used by
the core to fetch instructions. The targets of this bus are the internal flash memory,
SRAM1and SRAM2.
2.1.2

S1: CPU D-bus

This bus connects the data bus of the CPU core to the bus matrix. This bus is used by the
core for literal load and debug access. The targets of this bus are the internal flash memory,
SRAM1 and SRAM2.
2.1.3

S2: CPU S-bus

This bus connects the system bus of the CPU core to the bus matrix. This bus is used by the
core to access data located in a peripheral or SRAM area. The targets of this bus are the
SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the AHB3 peripherals including the APB3.
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Figure 1. System architecture

DMA1 DMA2
S4 S5
Bus matrix
RM0461 Rev 5
RM0461
Flash
memory FLASH
arbiter
SRAM1
SRAM2
AHB1
AHB2
AHB3
when remapped
MSv60753V1