Exti Rising Trigger Selection Register (Exti_Rtsr2) - STMicroelectronics STM32WLEx Reference Manual

Extended interrupts and event controller (EXTI)
Bit 13 PIF13: pending bit on event input 13
Bit 12 PIF12: pending bit on event input 12
Bit 11 PIF11: pending bit on event input 11
Bit 10 PIF10: pending bit on event input 10
Bit 9 PIF9: pending bit on event input 9
Bit 8 PIF8: pending bit on event input 8
Bit 7 PIF7: pending bit on event input 7
Bit 6 PIF6: pending bit on event input 6
Bit 5 PIF5: pending bit on event input 5
Bit 4 PIF4: pending bit on event input 4
Bit 3 PIF3: pending bit on event input 3
Bit 2 PIF2: pending bit on event input 2
Bit 1 PIF1: pending bit on event input 1
Bit 0 PIF0: pending bit on event input 0
14.6.5

EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. RT45 Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 RT45: rising trigger event configuration bit of configurable event input 45
Note: The configurable event inputs are edge triggered. No glitch must be generated on
Bits 12:3 Reserved, must be kept at reset value.
Bit 2 RT34: rising trigger event configuration bit of configurable event input 34
Bits 1:0 Reserved, must be kept at reset value.
414/1306
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
these inputs. If a rising edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0461 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. RT34
rw
RM0461
17 16
Res. Res.
1 0
Res. Res.