Table 193. Wwdg Internal Input/Output Signals; Figure 258. Watchdog Block Diagram - STMicroelectronics STM32WLEx Reference Manual

System window watchdog (WWDG)
29.3.1 WWDG block diagram
pclk
29.3.2 WWDG internal signals
Table 193
Signal name
wwdg_out_rst
wwdg_it
29.3.3 Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.
29.3.4 Controlling the down-counter
This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 259). The
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
the window register value and greater than 0x3F.
watchdog process.
882/1306

Figure 258. Watchdog block diagram

Register interface
W[6:0]
WWDG_CFR
WWDG_SR
readback
WWDG_CR
T[6:0]
7-bit DownCounter (CNT)
WDGTB
÷ 4096 ÷ 2
gives the list of WWDG internal signals.

Table 193. WWDG internal input/output signals

Signal type
pclk Digital input
Digital output
Digital output
WWDG configuration register (WWDG_CFR)
CMP = 1 when
T[6:0] > W[6:0]
Write to WWDG_CR
T[6:0]
cnt_out
preload
APB bus clock
WWDG reset signal output
WWDG early interrupt output
Figure 259
RM0461 Rev 5
WWDG
wwdg_out_rst
WDGA
T6
EWI wwdg_it
EWIF
Description
contains the high limit of the
describes the window
RM0461
MS47214V1