Exti Event Mask Register (Exti_Emr1) - STMicroelectronics STM32WLEx Reference Manual

RM0461
Bits 31:0 IM[31:0]: wakeup with interrupt mask on event input x (x= 31 to 0)
14.6.10

EXTI event mask register (EXTI_EMR1)

Address offset: 0x084
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
EM15 EM14 EM13 EM12
rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 EM22: wakeup with event generation mask on event input 22
Bit 21 EM21: wakeup with event generation mask on event input 21
Bit 20 EM20: wakeup with event generation mask on event input 20
Bit 19 EM19: wakeup with event generation mask on event input 19
Bit 18 EM18: wakeup with event generation mask on event input 18
Bit 17 EM17: wakeup with event generation mask on event input 17
Bit 16 Reserved, must be kept at reset value.
Bit 15 EM15: wakeup with event generation mask on event input 15
Bit 14 EM14: wakeup with event generation mask on event input 14
Bit 13 EM13: wakeup with event generation mask on event input 13
Bit 12 EM12: wakeup with event generation mask on event input 12
Bit 11 EM11: wakeup with event generation mask on event input 11
Bit 10 EM10: wakeup with event generation mask on event input 10
Bit 9 EM9: wakeup with event generation mask on event input 19
Bit 8 EM8: wakeup with event generation mask on event input 8
Bit 7 EM7: wakeup with event generation mask on event input 7
Bit 6 EM6: wakeup with event generation mask on event input 6
Bit 5 EM5: wakeup with event generation mask on event input 5
Bit 4 EM4: wakeup with event generation mask on event input 4
Bit 3 EM3: wakeup with event generation mask on event input 3
For each bit of this field:
0: Wakeup with interrupt request from line x is masked.
1: Wakeup with Interrupt request from line x is unmasked.
28 27 26 25
Res. Res. Res.
12 11 10 9
EM11 EM10 EM9
rw rw rw rw
0: Event request from line 22 is masked.
1: Event request from line 22 is unmasked.
Extended interrupts and event controller (EXTI)
24 23 22
Res. Res. EM22 EM21
rw
8 7 6
EM8 EM7 EM6
rw rw rw
RM0461 Rev 5
21 20 19 18
EM20 EM19 EM18
rw rw rw rw
5 4 3 2
EM5 EM4 EM3 EM2
rw rw rw rw
17 16
EM17 Res.
rw
1 0
EM1 EM0
rw rw
417/1306
419