STMicroelectronics STM32WLEx Reference Manual page 374

Direct memory access controller (DMA)
Bit 14 CHTIF4: half transfer flag clear for channel 4
Bit 13 CTCIF4: transfer complete flag clear for channel 4
Bit 12 CGIF4: global interrupt flag clear for channel 4
Bit 11 CTEIF3: transfer error flag clear for channel 3
Bit 10 CHTIF3: half transfer flag clear for channel 3
Bit 9 CTCIF3: transfer complete flag clear for channel 3
Bit 8 CGIF3: global interrupt flag clear for channel 3
Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1
11.6.3 DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
This register contains privileged information: the privileged state of the channel x (PRIV
control bit).
Modifying the PRIV bit must be performed by a privileged write access to this register.
Except PRIV control bit, any other register field is non-readable by an unprivileged software
if the PRIV bit is set.
The register fields/bits PRIV, MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC,
and DIR are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
MEM2
Res. PL[1:0]
MEM
rw rw rw
374/1306
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
MSIZE[1:0] PSIZE[1:0]
rw rw rw rw
RM0461 Rev 5
23 22 21 20
Res. Res. Res. PRIV
rw
7 6 5
MINC PINC CIRC DIR
rw rw rw rw
19 18 17
Res. Res. Res.
4 3 2 1
TEIE HTIE TCIE
rw rw rw
RM0461
16
Res.
0
EN
rw