STMicroelectronics STM32WLEx Reference Manual page 833

RM0461
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Bit 11 OSSR: Off-state selection for Run mode
This bit is used when MOE=1 on channels that have a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is implemented
in the timer.
See OC/OCN enable description for more details
enable register (TIMx_CCER)(x = 16 to 17) on page
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
is taken over by the GPIO, which forces a Hi-Z state)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
or CCxNE=1 (the output is still controlled by the timer).
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
not be active)
in TIMx_BDTR register).
in TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
TIMx_BDTR register).
Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
bits in TIMx_BDTR register).
General-purpose timers (TIM16/TIM17)
(Section 25.4.8: TIMx capture/compare
RM0461 Rev 5
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